Method of forming package-on-package structure

ABSTRACT

A method of forming a package-on-package (POP) structure is provided. A laser drilling is performed on a mold compound of a first semiconductor package to form a plurality of through holes in the mold compound. A conductive layer is formed on the mold compound such that the mold compound is covered by a conductive material and the through holes are filled with the conductive material. The layer of the conductive material is grinded to expose the mold compound. A second semiconductor package is stacked on the first semiconductor package such that a plurality of metal bumps of the second semiconductor package attach to the conductive material filled in the through holes.

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of U.S. Provisional Application No.62/410,851, filed on Oct. 21, 2016, the contents of which areincorporated herein in their entirety.

BACKGROUND OF THE INVENTION 1. Field of the Invention

The present invention relates to a packaging method, and moreparticularly, to a method of forming a package-on-package (POP)structure.

2. Description of the Prior Art

Package-on-package (POP) is now the fastest growing semiconductorpackage technology since it is a cost-effective solution to high-densitysystem integrated in a single package. In a POP structure, variouspackages are integrated in a single semiconductor package to reduce thesize. A conventional POP structure usually uses solder balls, solderpillars or copper pillars to connect a first package to a second packageby using surface mount technology (SMT) or by performing a reflowprocess. A plurality of packages can therefore be integrated into onepackage so as to reduce their size and lower the complexity ofcircuitry. However, it is still difficult to reduce the thickness of apackage. Since a POP structure includes at least two packages stackingonto one another, a common problem is that the thickness of a POPstructure is too large and difficult to be reduced. For applicationssuch as mobile devices, a large POP structure may be difficult to beembedded in a small device. Hence, a solution for reducing the thicknessof a package structure is required in the field.

SUMMARY OF THE INVENTION

An embodiment provides a method of forming a package-on-package (POP)structure. The method comprises performing a laser drilling on a moldcompound of a first semiconductor package to form a plurality of throughholes in the mold compound, forming a conductive layer on the moldcompound such that the mold compound is covered by a conductive materialand the through holes are filled with the conductive material, grindingthe conductive layer to expose the mold compound, and stacking a secondsemiconductor package on the first semiconductor package such that aplurality of metal bumps of the second semiconductor package attach tothe conductive material filled in the through holes.

These and other objectives of the present invention will no doubt becomeobvious to those of ordinary skill in the art after reading thefollowing detailed description of the preferred embodiment that isillustrated in the various figures and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1 to 6 are component cross-sectional views showing correspondingprocessing steps of the method of forming a package-on-package (POP)structure according to a first embodiment of the present invention.

FIGS. 7 to 12 are component cross-sectional views showing correspondingprocessing steps of the method of forming a POP structure according to asecond embodiment of the present invention.

DETAILED DESCRIPTION

With reference to the attached drawings, the present invention isdescribed by means of the embodiment(s) below where the attacheddrawings are simplified for illustration purposes only to illustrate thestructures or methods of the present invention by describing therelationships between the components and assembly in the presentinvention. Therefore, the components shown in the figures are notexpressed with the actual numbers, actual shapes, actual dimensions, norwith the actual ratio. Some of the dimensions or dimension ratios havebeen enlarged or simplified to provide a better illustration. The actualnumbers, actual shapes, or actual dimension ratios can be selectivelydesigned and disposed and the detail component layouts may be morecomplicated.

According to a first embodiment of the present invention, a method offorming a package-on-package (POP) structure is illustrated in FIGS. 1to 6 for a cross-sectional view.

As shown in FIG. 1, a first semiconductor package 100 is provided. Thefirst semiconductor package 100 comprises a first die 110, a moldcompound 120, a plurality of conductive pads 132, a substrate 140 and aplurality of metal bumps 150. The first die 110 and the conductive pads132 are disposed on the substrate 140 and encapsulated by the moldcompound 120. The metal bumps 150 are formed below the substrate 140. Inthe embodiment, the first semiconductor package 100 is a flip-chippackage, but the present invention is not limited thereto. The first die110 has a plurality of pillar bumps 112 disposed on the substrate 140and electrically connected to some of the metal bumps 150. The pillarbumps 112 are used as an I/O interface of the first die 110. Thesubstrate 140 may comprise a pad mask layer 130 and a plurality ofconductive pillars 142. The conductive pillars 142 are formed in thesubstrate 140 and pass through the substrate 140. Some of the metalbumps 150 are electrically connected to the conductive pads 132 via theconductive pillars 142. In the embodiment, the first semiconductorpackage 100 may be a fan-out package.

As shown in FIG. 2, a laser drilling is performed on the mold compound120 to form a plurality of through holes 122 in the mold compound 120,such that the conductive pads 132 are exposed on bottoms of the throughholes 122.

As shown in FIG. 3, a conductive layer 160 is formed on the moldcompound 120 such that the mold compound 120 is covered by a conductivematerial and the through holes 122 are filled with the conductivematerial. The conductive material may be copper (Cu), gold (Au) or acopper gold (Au-Cu) alloy. The conductive layer 160 may be formed on themold compound 120 by sputtering or electroplating the conductivematerial on the mold compound 120.

As shown in FIG. 4, the conductive layer 160 is grinded to expose themold compound 120. Accordingly, the conductive material filled in thethrough holes 122 forms a plurality of through hole vias 160A. Thethrough hole vias 160A are in contact with the conductive pads 132. Aheight H of each through hole via 160A may range from 200 micrometers to300 micrometers. A distance D between bottoms of two adjacent throughhole vias 160A may be less than 300 micrometers. In another embodiment,the mold compound 120 may be grinded when grinding the conductive layer160. Since the conductive layer 160 and the mold compound 120 may begrinded, the thickness of the first semiconductor package 100 may bereduced. In another embodiment, the substrate 140 of the firstsemiconductor package 100 may be removed after the through hole vias160A are formed. Accordingly, the thickness of the first semiconductorpackage 100 may be further reduced.

As shown in FIGS. 5 and 6, a second semiconductor package 200 is stackedon the first semiconductor package 100. A plurality of metal bumps 250of the second semiconductor package 200 are attached to the through holevias 160A when the second semiconductor package 200 is stacked on thefirst semiconductor package 100. The metal bumps 250 of the secondsemiconductor package 200 may be attached to the exposed surface ofthrough hole vias 160A by performing a reflow soldering process. As aresult, the first semiconductor package 100 and the second semiconductorpackage 200 are integrated as a package-on-package (POP) structure 300.Since the through holes 122 are formed by performing a laser drilling,the POP structure 300 would be a fine pitch package.

In the embodiment, the second semiconductor package 200 may be a fan-outpackage and/or a flip-chip package, but the present invention is notlimited thereto. The second semiconductor package 200 comprises a seconddie 210, a mold compound 220, a substrate 240 and the metal bumps 250.The second die 210 is disposed on the substrate 240 and encapsulated bythe mold compound 220. The metal bumps 250 are formed below thesubstrate 240. The second die 210 is electrically connected to some ofthe metal bumps 150 of the first semiconductor package 100 via the metalbumps 250 of the second semiconductor package 200, the through hole vias160A and the conductive circuit of the substrate 140. The second die 210comprises a plurality of pillar bumps 212. The conductive pillars 242are disposed in the substrate 240 and electrically connected to themetal bumps 250.

According to a second embodiment of the present invention, anothermethod of forming a POP structure is illustrated in FIGS. 7 to 12 for across-sectional view. The same reference numbers used in the firstembodiment and the second embodiment represent the same elements.

As shown in FIG. 7, a first semiconductor package 400 according toanother embodiment is provided. The major difference between the twosemiconductor packages 100 and 400 is that the first die 110 in FIG. 7is coupled to the substrate 140 through wire bonding. The first die 110is coupled to a circuitry formed in the substrate 140 via a plurality ofwires 114. The circuitry formed in the substrate 140 is electricallyconnected to some of the metal bumps 150.

As shown in FIG. 8, a laser drilling is performed on the mold compound120 to form a plurality of through holes 122 in the mold compound 120,such that the conductive pads 132 are exposed on bottoms of the throughholes 122.

As shown in FIG. 9, a conductive layer 160 is form on the mold compound120 such that the through holes 122 are filled with the conductivematerial and the mold compound 120 is covered by the conductivematerial.

As shown in FIG. 10, the conductive layer 160 is grinded to expose themold compound 120. Accordingly, the conductive material filled in thethrough holes 122 forms a plurality of through hole vias 160A. Thethrough hole vias 160A may be in contact with the conductive pads 132. Aheight H of each through hole via 160A may be range from 200 micrometersto 300 micrometers. A distance D between bottoms of two adjacent throughhole vias 160A may be less than 300 micrometers. In another embodiment,the mold compound 120 may be grinded when grinding the conductive layer160. Since the conductive layer 160 and the mold compound 120 may begrinded, the thickness of the first semiconductor package 400 may bereduced.

As shown in FIGS. 11 and 12, the second semiconductor package 200 isstacked on the first semiconductor package 400. A plurality of metalbumps 250 of the second semiconductor package 200 are attached to thethrough hole vias 160A when the second semiconductor package 200 isstacked on the first semiconductor package 400. The metal bumps 250 ofthe second semiconductor package 200 may be bonded to the through holevias 160A of the first semiconductor package 400 by performing a reflowsoldering process. As a result, the first semiconductor package 400 andthe second semiconductor package 200 are integrated as apackage-on-package (POP) structure 500.

In summary, a laser drilling is performed to form a plurality of throughholes in the mold compound, and the through holes are filled with theconductive material to form a plurality of through hole vias. Thedistance between the bottoms of two adjacent through hole vias may beless than 300 micrometers. Thereby, the POP structure would be a finepitch package. Moreover, the conductive layer and the mold compound maybe grinded, and the substrate of the first semiconductor package may beremoved after the through hole vias are formed. Accordingly, thethickness of the POP structure would be reduced.

Those skilled in the art will readily observe that numerousmodifications and alterations of the device and method may be made whileretaining the teachings of the invention. Accordingly, the abovedisclosure should be construed as limited only by the metes and boundsof the appended claims.

1. A method of forming a package-on-package (POP) structure, the methodcomprising: performing a laser drilling on a mold compound of a firstsemiconductor package to form a plurality of through holes in the moldcompound; forming a conductive layer on the mold compound such that themold compound is covered by a conductive material and the through holesare filled with the conductive material; grinding the conductive layerto expose the mold compound; and stacking a second semiconductor packageon the first semiconductor package such that a plurality of metal bumpsof the second semiconductor package attach to the conductive materialfilled in the through holes.
 2. The method of claim 1, wherein formingthe conductive layer on the mold compound includes sputtering theconductive material on the mold compound.
 3. The method of claim 1,wherein forming the conductive layer on the mold compound includeselectroplating the conductive material on the mold compound.
 4. Themethod of claim 1, wherein the conductive material is copper.
 5. Themethod of claim 1, wherein the conductive material is gold.
 6. Themethod of claim 1, wherein the conductive material is a copper goldalloy.
 7. The method of claim 1, wherein the first semiconductor packageis a flip-chip package.
 8. The method of claim 1, wherein the firstsemiconductor package comprises a first die and a first substrate, acircuitry is formed in the first substrate, and the first die iselectrically connected to the circuitry via a plurality of bondingwires.
 9. The method of claim 1, wherein the first semiconductor packagecomprises a first die, a first substrate and a plurality of conductivepads, the first die is disposed on the first substrate and encapsulatedby the mold compound, and the conductive pads are exposed on bottoms ofthe through holes after performing the laser drilling.
 10. The method ofclaim 9, wherein the first semiconductor package further comprises aplurality of conductive pillars formed in the first substrate and aplurality of metal bumps formed below the first substrate, and theconductive pads are electrically connected to some of the metal bumps ofthe first semiconductor package via the conductive pillars.
 11. Themethod of claim 1, wherein the second semiconductor package comprises asecond die, the first semiconductor package comprises a first die, afirst substrate, a plurality of conductive pillars and a plurality ofmetal bumps, the first die is disposed on the first substrate andencapsulated by the mold compound, the conductive pillars are formed inthe first substrate, the metal bumps of the first semiconductor packageare formed below the first substrate, the conductive material filled inthe through holes forms a plurality of through hole vias, and the seconddie is electrically connected to some of the metal bumps of the firstsemiconductor package via the metal bumps of the second semiconductorpackage, the through hole vias and the conductive pillars.
 12. Themethod of claim 11, wherein the second semiconductor package furthercomprises a plurality of pillar bumps electrically connected to themetal bumps of the second semiconductor package.
 13. The method of claim11, wherein the second semiconductor package further comprises a secondsubstrate, the second die is disposed on the second substrate, and themetal bumps of the second semiconductor package are formed below thesecond substrate.
 14. The method of claim 1, wherein the conductivematerial filled in the through holes forms a plurality of through holevias, and a height of each through hole via is between 200 micrometersto 300 micrometers.
 15. The method of claim 1, wherein the conductivematerial filled in the through holes forms a plurality of through holevias, and a distance between bottoms of two adjacent through hole viasis less than 300 micrometers.
 16. The method of claim 1, wherein themold compound is epoxy molding compound.
 17. The method of claim 1,wherein the second semiconductor package is a flip-chip package.
 18. Themethod of claim 1, wherein the first semiconductor package is a fan-outpackage.
 19. The method of claim 1, wherein the second semiconductorpackage is a fan-out package.
 20. The method of claim 1, wherein theconductive material filled in the through holes forms a plurality ofthrough hole vias, and the metal bumps of the second semiconductorpackage are bonded to the through hole vias by performing a reflowsoldering process.